Gpu Physical Design Engineer Lead

Intel Retiree Medical Plan Trust

Folsom, California, US
$190,610.00-269,100.00 usd; not specified; health,...
Hybrid
Soc level physical design and optimization
Floor-planning, clocking, synthesis
Static timing analysis, formal verification
The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc

Job Summary

  • The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc.
  • Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc.

Salary

$190,610.00-269,100.00 USD; Not specified; health, retirement, and vacation

Skills & Requirements

Must-have

  • SoC level physical design and optimization
  • Floor-planning, Clocking, Synthesis
  • Static Timing Analysis, Formal Verification
  • Layout Verification, Quality Assurance
  • Unix/Linux, Perl and TCL scripting

Nice-to-have

  • Leading a small team
  • Interacting with architecture and design teams
  • Defining design requirements
  • SoC integration methodologies
  • Clock Construction Methodology and Power estimation

Key Requirements

  • Bachelor’s in Electrical/Computer Engineering with 9+ years experience
  • Master's in Electrical/Computer Engineering with 6+ years experience
  • Experience in Logic Design, VLSI/ASIC Design
  • Experience in Computer Architecture
  • Current Industry Experience in ASIC design flows

Work Rights

Not specified

Tailored Resume

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