Principal Engineer, Asic Verification - Ai/hpc Socs
Marvell Technology
Base: cad 145,800 - 194,400 py; bonus/equity: not ...
System verilog and uvm methodology experience
Pcie, noc, ddr, hbm verification expertise
10+ years design engineering with focus on verification
This role involves developing the architecture for functional verification environments including reference models and bus-functional monitors for complex AI/ML and Network processing SoCs
Job Summary
This role involves developing the architecture for functional verification environments including reference models and bus-functional monitors for complex AI/ML and Network processing SoCs.
Candidates will lead a geographically dispersed team in pre-silicon validation while collaborating with strategic Hyper scalar and Data Center customers.
The position offers competitive compensation within an environment of shared collaboration, transparency, and inclusivity focused on purposeful innovation.
Matching Summary
This role involves developing the architecture for functional verification environments including reference models and bus-functional monitors for complex AI/ML and Network processing SoCs.
Salary
Base: CAD 145,800 - 194,400 per annum; Bonus/Equity: Not specified; Benefits: Competitive compensation and great benefits
Skills & Requirements
Must-have
System Verilog and UVM methodology experience
PCIe, NOC, DDR, HBM verification expertise
10+ years design engineering with focus on verification
Nice-to-have
Leadership for geographically dispersed teams
Strong Python or Perl scripting skills
Object-oriented design implementation
Key Requirements
Bachelor's degree with 12+ years experience
Master's or PhD with 10+ years experience
Eligibility to access export-controlled information
Work Rights
Must be US citizen, lawful permanent resident, or protected individual as defined by 8 U.S.C. 1324b(a)(3)