Senior Post Silicon Dft Engineer

Intel Corporation

Haifa, Israel
Hybrid
Dft design engineer
Post-silicon enablement
Scan and array infrastructure
This position is in Intel’s “center of excellence” for Silicon debug supporting Client products

Job Summary

  • This position is in Intel’s “center of excellence” for Silicon debug supporting Client products.
  • This team resolves product quality and performance issues blocking products from meeting production requirements with a combination of design and manufacturing problem solving expertise.
  • This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Matching Summary

This position is in Intel’s “center of excellence” for Silicon debug supporting Client products.

Skills & Requirements

Must-have

  • DFT Design Engineer
  • post-Silicon enablement
  • Scan and Array infrastructure
  • JTAG/TAP debug
  • yield loss diagnosis

Nice-to-have

  • state of the art methodologies
  • hands-on self-motivated problem solver
  • digital circuit design methodology
  • power-on and reset flow

Key Requirements

  • BSC or MSC degree in Engineering
  • Previous semiconductor circuit design experience
  • Strong verbal and written communication skills (English)

Work Rights

Not specified

Tailored Resume

Cover Letter