Asic Engineer | Physical Design | 4+ Years |

Cisco UK

Bangalore, India
Rtl to gds implementation flow
Hierarchical floor planning and place & route
Timing closure and power integrity analysis
Join the Cisco SiliconOne team to craft groundbreaking enterprise and service provider solutions using advanced chip technologies

Job Summary

  • Join the Cisco SiliconOne team to craft groundbreaking enterprise and service provider solutions using advanced chip technologies.
  • Drive the backend process through the entire RTL 2 GDS implementation flow including hierarchical floor planning, timing closure, and power integrity.
  • Work in a unique startup culture within a top-tier networking company with exposure to silicon, hardware, software, and security aspects.

Matching Summary

Join the Cisco SiliconOne team to craft groundbreaking enterprise and service provider solutions using advanced chip technologies.

Skills & Requirements

Must-have

  • RTL to GDS implementation flow
  • Hierarchical floor planning and place & route
  • Timing closure and power integrity analysis
  • Experience with sub 16nm process nodes
  • Large design implementation >100M gates

Nice-to-have

  • Methodology automation and scripting
  • STA setup for multi-mode multi-corner designs
  • Debugging skills for implementation issues
  • Collaboration with EDA vendors and tool owners
  • Tweaker/Primetime based ECO flows

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 5+ years of experience in ASIC Physical implementation
  • Experience with large designs exceeding 100 million gates

Work Rights

Not specified

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