Principal Design Engineer – Ai Soc / Subsystem Lead

Intel

Folsom, California, United States
Base: $220,920.00-311,890.00 usd annually; bonus/e...
Hybrid
10+ years of engineering experience
7+ years rtl design and implementation
Asic/soc development expertise
Intel is seeking a Principal Design Engineer for its AI SoC organization, responsible for leading the design and validation of complex SoC IP blocks and subsystems for AI applications. The ideal candidate should possess extensive experience in RTL design and implementation, as well as strong technical and communication skills

Job Summary

  • This role offers the opportunity to shape the future of AI hardware by defining and validating complex SoC IP blocks for next-generation solutions.
  • The successful candidate will collaborate across architecture, verification, and physical design teams to deliver high-quality silicon meeting stringent power and performance targets.
  • Intel provides a competitive compensation package including stock bonuses, health benefits, and a hybrid work model allowing time split between on-site and off-site work.

Matching Summary

Match Score: 85

Intel is seeking a Principal Design Engineer for its AI SoC organization, responsible for leading the design and validation of complex SoC IP blocks and subsystems for AI applications. The ideal candidate should possess extensive experience in RTL design and implementation, as well as strong technical and communication skills.

Salary

Base: $220,920.00-311,890.00 USD annually; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs offered

Skills & Requirements

Must-have

  • 10+ years of engineering experience
  • 7+ years RTL design and implementation
  • ASIC/SoC development expertise
  • Verilog/SystemVerilog proficiency
  • Microarchitecture definition skills
  • Timing closure and constraints
  • Post-silicon validation and debug

Nice-to-have

  • Mentorship of junior engineers
  • Cross-functional collaboration skills
  • Strong communication abilities
  • Secure development practices knowledge
  • Python/TCL scripting for automation
  • Experience with multicore CPU subsystems
  • Familiarity with AXI/AHB protocols

Key Requirements

  • Bachelor's or Master's degree in EE, Computer Engineering, or CS
  • Minimum 10 years of total professional experience
  • Minimum 7 years of specific RTL design experience
  • Position of Trust requiring extended background investigation

Work Rights

Not specified

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