Verification Engineer (remote)

Fortifyiq

Remote
Fully remote
Uvm-based verification environments
Verilog/systemverilog and uvm
Linux and eda tools
Fortifyiq is looking for a remote Verification Engineer to validate advanced chip designs by creating UVM environments, writing test plans, and collaborating with cross-functional teams. The ideal candidate should have a strong background in electrical engineering or computer science, along with proficiency in Verilog/SystemVerilog and UVM

Job Summary

  • Contribute to the validation of advanced chip designs by creating and maintaining UVM environments.
  • Write tests and ensure functional coverage for high-performance silicon products.
  • Collaborate closely with architecture, design, and circuit teams to meet quality and schedule goals.

Matching Summary

Match Score: 85

Fortifyiq is looking for a remote Verification Engineer to validate advanced chip designs by creating UVM environments, writing test plans, and collaborating with cross-functional teams. The ideal candidate should have a strong background in electrical engineering or computer science, along with proficiency in Verilog/SystemVerilog and UVM.

Skills & Requirements

Must-have

  • UVM-based verification environments
  • Verilog/SystemVerilog and UVM
  • Linux and EDA tools
  • functional and code coverage analysis

Nice-to-have

  • strong problem-solving skills
  • excellent teamwork and communication

Key Requirements

  • BSEE/MSEE or equivalent
  • Proficient in Verilog/SystemVerilog and UVM
  • Comfortable working in Linux
  • Solid grasp of verification methodologies

Work Rights

Not specified

Tailored Resume

Cover Letter