Team Lead Vérification Asic R&d (f/h)

Atos SE

Valbonne, France
On-site
Uvm verification methodology
Constraint-random/coverage-driven
Systemverilog/c++ development
Participate in the verification of complex ASICs for high-end and high-performance servers

Job Summary

  • Participate in the verification of complex ASICs for high-end and high-performance servers.
  • Develop verification environments, tests, and coverage models using UVM-SystemVerilog/C++.
  • Benefit from tailored training, flexible remote work options, and a competitive compensation package.

Matching Summary

Participate in the verification of complex ASICs for high-end and high-performance servers.

Skills & Requirements

Must-have

  • UVM verification methodology
  • Constraint-Random/Coverage-Driven
  • SystemVerilog/C++ development
  • ASIC/SoC/IP verification experience
  • Simulation tools and coverage tracking

Nice-to-have

  • Excellent communication skills
  • Team collaboration
  • Adaptability and multitasking
  • Bilingual French/English proficiency

Key Requirements

  • Experience in complex SoC/ASIC and IP verification
  • Experience with UVM methodology
  • Experience in Constraint-Random/Coverage-Driven environments
  • Proficiency in SystemVerilog/C++ and OOP
  • Familiarity with simulation and coverage tools
  • Problem-solving skills

Work Rights

Not specified

Tailored Resume

Cover Letter