Sr/ DFT Engineer (Silicon Design)

ETHOS TECH ONE PTE. LTD.

Islandwide, Singapore
Dft implementation on hard-ips in fpgas
Scan compression and stuck-at fault models
Debugging scan/mbist pattern issues on bench/ate
The role involves developing and implementing DFT schemes on hard-IPs within FPGAs to ensure correct structure insertion

Job Summary

  • The role involves developing and implementing DFT schemes on hard-IPs within FPGAs to ensure correct structure insertion.
  • Candidates will be responsible for debugging scan and mbist pattern issues using bench and ATE environments to root cause problems.
  • The position requires assisting in diagnosis and yield enhancement throughout the product lifecycle while working with a global team.

Matching Summary

Match Score: 85

The role involves developing and implementing DFT schemes on hard-IPs within FPGAs to ensure correct structure insertion.

Skills & Requirements

Must-have

  • DFT implementation on hard-IPs in FPGAs
  • Scan Compression and Stuck-at fault models
  • Debugging scan/mbist pattern issues on bench/ATE
  • Verilog logic design and synthesis experience
  • ATPG tools for At-Speed and Path-Delay testing

Nice-to-have

  • Knowledge of MBIST and FPGA synthesis flow
  • Post-silicon debug and bench setup experience
  • Linux environment and scripting languages
  • Cross-continent team collaboration skills

Key Requirements

  • BS or MS in Electrical/Electronic/Computer Engineering
  • 1 or more years of DFT experience
  • Experience with complex chip-level DFT architecture

Work Rights

Not specified

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