Testing Engineer Iv - Pcie

Astreya GmbH

Base: $98,040.00 - $154,800.00 usd; bonus/equity: ...
Not specified
Pcie gen 4/5/6 protocol expertise
Uvm testbench development experience
High-speed io silicon bring-up
Astreya GmbH is seeking an experienced Hardware Verification & Validation Engineer specializing in PCIe to oversee both pre-silicon and post-silicon testing of ASIC designs. The position requires strong expertise in high-speed I/O, UVM testbench architecture, and cross-functional collaboration. Candidates should have significant experience in ASIC development and programming skills in Python and C/C++

Job Summary

  • This role bridges the gap between pre-silicon verification and post-silicon lab validation for next-generation PCIe interfaces.
  • Candidates will architect robust UVM testbenches to rigorously test complex PCIe protocol behaviors across Gen 4, 5, and 6.
  • The company offers comprehensive benefits including medical, dental, vision, 401k, and tuition reimbursement.

Matching Summary

Match Score: 85

Astreya GmbH is seeking an experienced Hardware Verification & Validation Engineer specializing in PCIe to oversee both pre-silicon and post-silicon testing of ASIC designs. The position requires strong expertise in high-speed I/O, UVM testbench architecture, and cross-functional collaboration. Candidates should have significant experience in ASIC development and programming skills in Python and C/C++.

Salary

Base: $98,040.00 - $154,800.00 USD; Bonus/Equity: Not specified (discretionary); Benefits: Comprehensive medical, dental, vision, 401k included

Skills & Requirements

Must-have

  • PCIe Gen 4/5/6 protocol expertise
  • UVM testbench development experience
  • High-speed IO silicon bring-up
  • Python or C++ automation scripting
  • Oscilloscope and BERT usage

Nice-to-have

  • Cross-functional debugging skills
  • Linux environment familiarity
  • JTAG and Trace32 tool proficiency
  • Root cause analysis in physical labs

Key Requirements

  • BS or MS in Electrical Engineering
  • 6-8+ years of ASIC development experience
  • In-depth knowledge of PCIe protocol layers

Work Rights

Not specified

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