Lead the verification of cutting-edge data center and networking silicon solutions, ensuring first-pass silicon success across DPUs, SmartNICs, and HPC platforms
Job Summary
Lead the verification of cutting-edge data center and networking silicon solutions, ensuring first-pass silicon success across DPUs, SmartNICs, and HPC platforms.
Architect scalable verification environments, drive test plans from concept to execution, and provide technical leadership across global teams.
Drive methodology and infrastructure improvements to accelerate coverage closure and reduce verification cycle times by 50% or more.
Matching Summary
Lead the verification of cutting-edge data center and networking silicon solutions, ensuring first-pass silicon success across DPUs, SmartNICs, and HPC platforms.
Salary
$221.5K - $326.3K USD
Skills & Requirements
Must-have
UVM-based scalable verification environments
PCIe Gen5/Gen6 protocols
Host interface subsystems verification
High-performance verification methodologies
ASIC/SoC design verification
Nice-to-have
Technical leadership and mentorship
Cross-functional alignment
Thought leadership in PCIe verification
Drive methodology improvements
Key Requirements
20+ years of experience in ASIC/SoC design verification
20+ years of experience in SystemVerilog, Verilog, UVM, OOP
20+ years of experience in debugging pre-silicon and post-silicon issues
10+ years of experience in a leadership role
Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field