Logic Design & Verification Engineer

Cisco UK

Caesarea, Israel
Rtl design experience
Verilog/systemverilog implementation
Uvm functional verification
Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation

Job Summary

  • Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
  • We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.

Skills & Requirements

Must-have

  • RTL design experience
  • Verilog/SystemVerilog implementation
  • UVM functional verification
  • debug and root-cause analysis
  • physical design collaboration

Nice-to-have

  • MATLAB simulations
  • mixed-signal systems
  • Clock Domain Crossing (CDC)

Key Requirements

  • B.Sc./M.Sc. in Electrical Engineering
  • 3+ years of relevant experience
  • RTL design experience
  • Familiarity with UVM

Work Rights

Not specified

Tailored Resume

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