Silicon Design Flow Methodology And Automation - Lec.
Altera Corporation
Penang, Malaysia
Logic equivalence check (lec)
Atpg model generation
Cadence conformal and/or synopsys formality
Define, develop, and maintain scalable automation, flows, and methodologies for silicon design verification and test enablement, focusing on Logic Equivalence Check (LEC) and ATPG model generation
Job Summary
Define, develop, and maintain scalable automation, flows, and methodologies for silicon design verification and test enablement, focusing on Logic Equivalence Check (LEC) and ATPG model generation.
Collaborate closely with design, ATPG, and CAD teams to deliver robust, automated solutions that improve productivity, correctness, DFT coverage, and simulation quality.
Own and develop end-to-end Logic Equivalence Check (LEC) flows using industry-standard tools and define, document, and maintain LEC methodologies across RTL-to-gate, gate-to-gate, and ECO verification stages.
Matching Summary
Define, develop, and maintain scalable automation, flows, and methodologies for silicon design verification and test enablement, focusing on Logic Equivalence Check (LEC) and ATPG model generation.
Skills & Requirements
Must-have
Logic Equivalence Check (LEC)
ATPG model generation
Cadence Conformal and/or Synopsys Formality
Tcl, Python, Perl, shell scripting
ECO verification flows
Nice-to-have
AI/ML techniques for productivity
version control systems (Git, Perforce)
cross-domain EDA experience
Key Requirements
5+ years of experience in silicon design automation
Bachelor’s or Master’s degree in Electrical Engineering or related field