Senior Asic Design - Cisco Silicon One

Cisco UK

Not specified; not specified; not specified
B.sc./m.sc. in electrical engineering
Rtl design experience with verilog/systemverilog
Familiarity with uvm and functional verification
Engineers cover the full spectrum of chip design including definition, architecture, micro-architecture, RTL design, verification, signoff, and validation

Job Summary

  • Engineers cover the full spectrum of chip design including definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
  • The team leverages cutting-edge silicon technologies to develop the largest-scale and most advanced devices for Cisco's future routing portfolio.
  • Candidates will collaborate with verification and physical design teams to resolve bugs, close timing, and support design methodology evolution.

Matching Summary

Engineers cover the full spectrum of chip design including definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.

Salary

Not specified; Not specified; Not specified

Skills & Requirements

Must-have

  • B.Sc./M.Sc. in Electrical Engineering
  • RTL design experience with Verilog/SystemVerilog
  • Familiarity with UVM and functional verification

Nice-to-have

  • Experience with MATLAB simulations
  • Knowledge of mixed-signal systems
  • Hands-on experience with Clock Domain Crossing

Key Requirements

  • B.Sc./M.Sc. degree from a top university
  • Proven RTL design experience
  • Top university background required

Work Rights

Not specified

Tailored Resume

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