Senior Hardware Asic Arch/design Engineer

NXP

Hyderabad, India
Ai inference chip architecture
Hardware-software co-optimization
Rtl implementation review
Define product features and own the architecture for compute, memory, interconnect, and high-speed interface subsystems in AI inference chips

Job Summary

  • Define product features and own the architecture for compute, memory, interconnect, and high-speed interface subsystems in AI inference chips.
  • Collaborate closely with software and RTL design teams to optimize hardware features for AI workloads and ensure architectural consistency.
  • Develop and maintain high-level architecture and performance models, validating predictions against RTL or emulation results.

Matching Summary

Define product features and own the architecture for compute, memory, interconnect, and high-speed interface subsystems in AI inference chips.

Skills & Requirements

Must-have

  • AI inference chip architecture
  • Hardware-software co-optimization
  • RTL implementation review
  • PPA analysis and trade-offs
  • High-level architecture modeling
  • AI workload understanding

Nice-to-have

  • Collaboration with physical-design teams
  • Programmability and debuggability features
  • Memory bandwidth optimization

Work Rights

Not specified

Tailored Resume

Cover Letter