Sr Principal Product Engineer – Memory Ip

Cadence

Base: $154,000 to $286,000 (california); bonus/equ...
Onsite
Post-silicon bring-up and debug experience
Memory protocol expertise ddr5 lpddr hbm gddr
Lab equipment usage for issue reproduction
This role serves as the primary technical contact for post-silicon bring-up and debug of Memory IP subsystems across advanced memory protocols

Job Summary

  • This role serves as the primary technical contact for post-silicon bring-up and debug of Memory IP subsystems across advanced memory protocols.
  • Candidates will collaborate with internal design and program management teams to resolve complex technical issues during silicon evaluations and customer demos.
  • The position offers opportunities to work on cutting-edge memory technologies impacting next-generation systems while receiving competitive compensation and benefits.

Matching Summary

This role serves as the primary technical contact for post-silicon bring-up and debug of Memory IP subsystems across advanced memory protocols.

Salary

Base: $154,000 to $286,000 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k) match, medical/dental/vision

Skills & Requirements

Must-have

  • Post-silicon bring-up and debug experience
  • Memory protocol expertise DDR5 LPDDR HBM GDDR
  • Lab equipment usage for issue reproduction
  • Schematic reading and SI/PI review skills
  • Customer SOC and system integration support

Nice-to-have

  • Exposure to STA and RTL flows
  • Familiarity with mixed-signal verification tools
  • Experience with AI-powered analytics tools
  • Strong presentation and communication skills
  • Collaboration with global engineering teams

Key Requirements

  • M.S. in Electrical/Computer Engineering or Ph.D.
  • 7+ years of relevant experience or 5+ years with Ph.D.
  • Hands-on experience with lab equipment for debugging
  • Ability to read schematics and participate in SI/PI reviews

Work Rights

Not specified

Tailored Resume

Cover Letter