Base: $173,800 - $257,190 py; bonus/equity: not sp...
Rtl-to-gdsii implementation experience
Hierarchical physical design strategies
Advanced-node cmos process expertise
This role offers the opportunity to drive improvements in physical design methodologies and flows for next-generation high-performance processor chips
Job Summary
This role offers the opportunity to drive improvements in physical design methodologies and flows for next-generation high-performance processor chips.
The successful candidate will own RTL-to-GDSII implementation for complex blocks including synthesis, floorplanning, PnR, and timing closure.
Marvell provides comprehensive benefits including an employee stock purchase plan, family support programs, and robust mental health resources.
Matching Summary
This role offers the opportunity to drive improvements in physical design methodologies and flows for next-generation high-performance processor chips.
Salary
Base: $173,800 - $257,190 per annum; Bonus/Equity: Not specified; Benefits: Stock purchase plan, family support, mental health resources
Skills & Requirements
Must-have
RTL-to-GDSII implementation experience
Hierarchical physical design strategies
Advanced-node CMOS process expertise
Timing closure and signoff proficiency
EDA tool automation with Tcl/Python
Nice-to-have
AI/ML-driven optimization familiarity
Cross-functional collaboration skills
Mentoring junior engineers capability
Global team engagement experience
Foundry technology constraint knowledge
Key Requirements
Bachelor's degree plus 5-10 years experience or Master's/PhD plus 3-5 years
Proven ability to tape out large high-performance chips
Eligibility to access export-controlled information under US law
Work Rights
Must be eligible to access export-controlled information (US citizens, lawful permanent residents, or protected individuals)