Senior Staff Verification Engineer

Altera

Bengaluru, Karnataka, India
Systemverilog and uvm verification environments
9+ years asic or fpga design verification experience
Constrained-random test case development
The role involves collaborating with architects and design engineers to define comprehensive verification strategies for FPGA acceleration projects

Job Summary

  • The role involves collaborating with architects and design engineers to define comprehensive verification strategies for FPGA acceleration projects.
  • Candidates will develop robust, reusable verification environments using SystemVerilog and UVM to exercise design functionality and uncover bugs.
  • The position requires defining and tracking functional and code coverage metrics to ensure verification completeness and drive closure.

Matching Summary

The role involves collaborating with architects and design engineers to define comprehensive verification strategies for FPGA acceleration projects.

Skills & Requirements

Must-have

  • SystemVerilog and UVM verification environments
  • 9+ years ASIC or FPGA design verification experience
  • Constrained-random test case development
  • Coverage-driven verification methodologies
  • Python or Perl scripting for automation

Nice-to-have

  • Familiarity with AMBA protocols like AXI and PCIe
  • Experience with formal verification methods
  • Strong analytical and problem-solving skills
  • Collaborative cross-functional team environment

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 9+ years of experience in ASIC or FPGA verification
  • Proficiency in Verilog, VHDL, and SystemVerilog

Work Rights

Not specified

Tailored Resume

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