This role involves developing and optimizing RTL logic design for DDRPHY IP to meet stringent power, performance, and timing goals while ensuring design integrity for physical implementation
Job Summary
This role involves developing and optimizing RTL logic design for DDRPHY IP to meet stringent power, performance, and timing goals while ensuring design integrity for physical implementation.
The position requires collaboration with verification, timing, physical teams, and project managers to ensure quality delivery and resource planning.
Intel offers a hybrid work model allowing employees to split time between on-site and remote work, supporting a flexible and inclusive work environment.
Matching Summary
This role involves developing and optimizing RTL logic design for DDRPHY IP to meet stringent power, performance, and timing goals while ensuring design integrity for physical implementation.
Skills & Requirements
Must-have
RTL coding and IP integration
SystemVerilog RTL implementation
Power and timing convergence
Static Timing Analysis support
Logic design quality checks
Cross-domain signal handling
Automation with Tcl/Tk/Perl/Python
Nice-to-have
DDR design experience
Knowledge of synthesis and place and route
Post-silicon testing familiarity
Strong communication skills
Coaching and team development
Secure development practices
Cross-site collaboration
Key Requirements
8+ years RTL coding experience
IP/Subsystem architecture knowledge
Experience with JEDEC high speed bus protocols
Good integration knowledge of analog and mixed signal designs
Experience with RTL lint, synthesis, equivalence and CDC checking