Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs
Job Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
As a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.
Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
Matching Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
Skills & Requirements
Must-have
Network on Chip IPs
RTL coding and simulation
System Verilog
VCS/Synopsys simulators
Lint and Synthesis
FPGA design and programming
Nice-to-have
Technical leadership and mentoring
Cross-functional team collaboration
Proactive problem-solving
Design challenge anticipation
Key Requirements
15+ years of related working experience
Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or related field
Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script