Asic Design Engineer, Sta

Cisco UK

San Jose, California, USA
Base: $152,500.00 - $219,200.00; bonus/equity: not...
Onsite
Asic design experience
Verilog/systemverilog programming
Closing timing at block, sub-chip, full-chip
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks

Job Summary

  • Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.
  • You'll work on closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while handling ECO tasks.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.

Salary

Base: $152,500.00 - $219,200.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k), paid parental leave, disability, life insurance, stock units, paid time off

Skills & Requirements

Must-have

  • ASIC Design experience
  • Verilog/SystemVerilog programming
  • closing timing at block, sub-chip, full-chip
  • quality checks (setup, hold, transition, noise)
  • handling ECO tasks

Nice-to-have

  • strong written and verbal communication
  • startup culture
  • collaboration with Physical Design team

Key Requirements

  • 5+ years ASIC Design experience (Bachelor's)
  • 3+ years ASIC Design experience (Master's)
  • Verilog/SystemVerilog programming experience
  • Prior STA experience is a plus

Work Rights

Not specified

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