Senior Principal Physical Design Engineer

NXP Semiconductors

Pune, India
Rtl to gdsii physical design
Floor planning, place and route
Clock tree synthesis, sta
Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII

Job Summary

  • Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII.
  • Drive and optimize design methodologies, flows, and scripts to improve efficiency, turnaround time, and design quality.
  • Mentor junior and mid-level engineers, providing technical guidance and fostering their growth within the physical design domain.

Matching Summary

Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII.

Skills & Requirements

Must-have

  • RTL to GDSII physical design
  • floor planning, place and route
  • clock tree synthesis, STA
  • DRC, LVS, formal verification
  • low-power design techniques
  • advanced process nodes tape-outs

Nice-to-have

  • design methodology optimization
  • EDA tool integration
  • technical initiative leadership
  • fast-paced collaborative environment

Key Requirements

  • 15+ years ASIC physical design experience
  • Bachelor's or Master's degree
  • Expertise in Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime
  • Proficiency in Tcl, Perl, Python scripting
  • Strong static timing analysis understanding
  • Hands-on low-power design experience

Work Rights

Not specified

Tailored Resume

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