Not specified; not specified; competitive compensa...
Ms or phd in ee or related field
Fluent in systemverilog rtl coding
Experience with multi-clock designs
Marvell's high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem providing low-power solutions for cloud data centers and AI networks
Job Summary
Marvell's high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem providing low-power solutions for cloud data centers and AI networks.
You will develop efficient RTL using SystemVerilog, integrate vendor IPs, and support back-end teams in timing closure and DFT implementation.
The role offers a collaborative environment where you can affect the trajectory of entire industries by driving the development of next-generation chip technologies.
Matching Summary
Marvell's high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem providing low-power solutions for cloud data centers and AI networks.
Salary
Not specified; Not specified; Competitive compensation and benefits described
Skills & Requirements
Must-have
MS or PhD in EE or related field
Fluent in SystemVerilog RTL coding
Experience with multi-clock designs
Synthesis and static timing closure skills
Formal verification and gate-level simulation
DFT test structures and IP integration
Front-end chip development tools proficiency
Nice-to-have
Design experience in high speed DSP products
Knowledge of Python Perl Tcl scripting
Strong can-do attitude and team player
Effective communication and presentation skills
Ability to adapt to rapidly changing environment
Key Requirements
MS/PhD degree in Electrical Engineering
Eligibility for US export control access
Proficiency in front-end design methodologies
Work Rights
Must be eligible for export-controlled information (US citizen, LPR, or protected individual)