High Speed Serdes Dsp Rtl Designer

Broadcom

California, United States
Base: $120,000 - $192,000; bonus/equity: discretio...
High speed adc based serdes rtl design
Verilog-hdl/system verilog coding
Pam4 dsp based serdes equalization
Broadcom is looking for a high-speed DSP SerDes RTL designer with expertise in high-speed serial interconnect architectures and design trade-offs

Job Summary

  • Broadcom is looking for a high-speed DSP SerDes RTL designer with expertise in high-speed serial interconnect architectures and design trade-offs.
  • The position offers a competitive salary range, discretionary annual bonus, equity awards, and a comprehensive benefits package including medical, dental, vision, 401(K) with company matching, and paid leave.
  • Broadcom is an equal opportunity employer committed to considering qualified applicants regardless of race, color, religion, sex, sexual orientation, national origin, disability, or other protected characteristics.

Matching Summary

Broadcom is looking for a high-speed DSP SerDes RTL designer with expertise in high-speed serial interconnect architectures and design trade-offs.

Salary

Base: $120,000 - $192,000; Bonus/Equity: Discretionary annual bonus and equity awards; Benefits: Medical, dental, vision, 401(K) with matching, ESPP, paid leave

Skills & Requirements

Must-have

  • High speed ADC based SerDes RTL design
  • Verilog-HDL/System Verilog coding
  • PAM4 DSP based SerDes equalization
  • Front end tools NCVerilog and NCSIM
  • Design for test and scan concept
  • Synthesis and static timing analysis
  • TSMC 7nm-2nm technology understanding

Nice-to-have

  • Micro architecture with AMBA BUS/I2C/SPI/UART
  • Signal Integrity and Power Integrity modeling
  • Verilog AMS simulation experience
  • Behavioral models of analog circuits
  • Strong analytical thinking and problem-solving
  • Organized and self-motivated
  • Effective cross-team collaboration

Key Requirements

  • MS or PhD in Electrical or Computer Engineering
  • 6+ years experience in SerDes RTL design
  • Experience with EDA integration and foundry PDK
  • Knowledge of scan and DFT friendly RTL writing
  • Experience with SDF annotated simulations
  • Understanding of power, area, and layout efforts
  • Must be organized and self-motivated

Work Rights

Not specified

Tailored Resume

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