We are seeking a Principal Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs, with end-to-end responsibility from block-level checks to final tape-out
Job Summary
We are seeking a Principal Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs, with end-to-end responsibility from block-level checks to final tape-out.
You will lead methodologies and execution for DRC, LVS, PERC and related reliability checks, Floor-planning by working closely with Place-n-route, analog/mixed-signal, timing analysis and CAD teams to ensure first-time-right silicon.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
Matching Summary
We are seeking a Principal Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs, with end-to-end responsibility from block-level checks to final tape-out.
Skills & Requirements
Must-have
Full-chip physical verification signoff
DRC, LVS, ERC, PERC, ANT/ESD checks
Develop and optimize PV flows and scripts
PERC reliability rule checks
Floorplanning and power grid planning
Debug complex DRC/LVS/PERC violations
Siemens Calibre, Synopsys IC Validator
Nice-to-have
Cross-functional technical closure
Mentor and guide junior engineers
Technical interface to foundry and EDA vendors
Familiarity with DFM/DFY checks
Key Requirements
10-15+ years of experience in physical verification
Bachelor’s or Master’s degree in Electrical/Electronics Engineering
Proven experience owning DRC/LVS/PERC signoff for 5 nm (or sub-7 nm) production tape-out
Solid scripting skills in Python, Perl, Tcl, or Unix shell