Asic Design Verification Engineer

Cisco UK

San Jose, California, USA
Base: $152,500.00 - $219,200.00 (us/canada); bonus...
System verilog and uvm
Asic design and verification processes
Debug, methodology, and tools
You will architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips

Job Summary

  • You will architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips.
  • Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco’s hardware platforms.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

You will architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips.

Salary

Base: $152,500.00 - $219,200.00 (US/Canada); Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k), paid parental leave, etc.

Skills & Requirements

Must-have

  • System Verilog and UVM
  • ASIC design and verification processes
  • debug, methodology, and tools
  • verifying blocks/clusters/full chip level
  • Hands on debugging experience

Nice-to-have

  • PCIe and AXI protocol knowledge
  • Linux, C/C++, and/or Python/Perl
  • Networking experience
  • Formal verification experience
  • post-silicon lab bring-up

Key Requirements

  • Bachelor's degree and 5+ years experience
  • Master's degree and 3+ years experience
  • PhD and 1+ year experience
  • Experience in System Verilog and UVM
  • Experience with ASIC design and verification processes
  • Experience verifying blocks/clusters/full chip level

Work Rights

Not specified

Tailored Resume

Cover Letter