Praktikum Im Bereich Fpga-entwicklung (m/w/x)

Carl Zeiss Pty Ltd

Jena, Germany
On-site
Vhdl module generation in python
Integration into existing vhdl design
Equivalence testing with questasim
Carl Zeiss Pty Ltd is offering an internship opportunity in FPGA development in Jena, Germany, focusing on designing and implementing VHDL modules and simulation verification. The role is ideal for engineering students with programming skills in Python and VHDL, alongside strong analytical and communication abilities

Job Summary

  • Combine studies and practical experience in exciting projects.
  • Design and implement codegenerators for automatic VHDL module generation in Python.
  • Verify and synthesize VHDL code for a representative FPGA platform.

Matching Summary

Match Score: 85

Carl Zeiss Pty Ltd is offering an internship opportunity in FPGA development in Jena, Germany, focusing on designing and implementing VHDL modules and simulation verification. The role is ideal for engineering students with programming skills in Python and VHDL, alongside strong analytical and communication abilities.

Skills & Requirements

Must-have

  • VHDL module generation in Python
  • Integration into existing VHDL design
  • Equivalence testing with QuestaSim
  • VHDL code synthesis for FPGA

Nice-to-have

  • Structured and analytical thinking
  • Good organizational skills
  • Good communication skills

Key Requirements

  • Studies in Engineering, Informatics, or similar
  • Programming skills in Python and VHDL
  • Good German and English language skills

Work Rights

Not specified

Tailored Resume

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