Emir/esd Engineer

Cisco UK

Armenia
Not specified (assumed to be hybrid based on cisco's general practices).
Asic design and verification experience
Rtl-to-gdsii physical implementation flow
Finfet technology schematic and layout
Cisco UK is seeking an Emir/esd Engineer to join their ASIC Physical Design Team in Armenia, focusing on enhancing chip design through EMIR and ESD analysis. The role requires a solid background in ASIC design, particularly in FinFET technologies, and offers a collaborative environment aimed at driving innovation in silicon technology

Job Summary

  • Drive Cisco's silicon innovation by performing comprehensive chip-level EMIR and ESD analysis to ensure the reliability of next-generation designs.
  • Collaborate with package teams, block owners, EDA tool vendors, and flow teams to optimize design fixes and enhance sign-off methodologies.
  • Join a highly skilled ASIC Physical Design Team focused on advancing power, performance, and reliability in silicon solutions shaping the future of connectivity.

Matching Summary

Match Score: 85

Cisco UK is seeking an Emir/esd Engineer to join their ASIC Physical Design Team in Armenia, focusing on enhancing chip design through EMIR and ESD analysis. The role requires a solid background in ASIC design, particularly in FinFET technologies, and offers a collaborative environment aimed at driving innovation in silicon technology.

Skills & Requirements

Must-have

  • ASIC design and verification experience
  • RTL-to-GDSII physical implementation flow
  • FinFET technology schematic and layout
  • Deep submicron CMOS technology knowledge
  • Power grid performance optimization

Nice-to-have

  • ESD protection concepts and implementation
  • Experience with Synopsys, Cadence, or Siemens tools
  • Strong scripting skills in Python, TCL, or Bash
  • Collaboration with cross-functional teams and vendors
  • Full-chip physical design and tape-out process experience

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering or Computer Science
  • Minimum 3 years ASIC design and verification experience

Work Rights

Not specified

Tailored Resume

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