Bachelor's, master's or ph.d. in electronics engineering
8 years experience in design verification with uvm
Strong proficiency in system verilog and uvm testbench development
The role involves validating next-generation architectural features for Intel's Power Management Controller IP through comprehensive test planning and execution
Job Summary
The role involves validating next-generation architectural features for Intel's Power Management Controller IP through comprehensive test planning and execution.
Candidates will collaborate closely with IP architects to define verification strategies and develop robust testbenches from the ground up using UVM.
This position requires cross-organizational influence with manufacturing partners and deep debugging skills to resolve complex system platform issues.
Matching Summary
The role involves validating next-generation architectural features for Intel's Power Management Controller IP through comprehensive test planning and execution.
Skills & Requirements
Must-have
Bachelor's, Master's or Ph.D. in Electronics Engineering
8 years experience in design verification with UVM
Strong proficiency in System Verilog and UVM testbench development
Experience building RTL models and verification components
Nice-to-have
Familiarity with Formal Property verification methods
Knowledge of ACPI spec and power management protocols
Experience with Assembly language and embedded firmware
Proficiency in Python and Perl scripting languages