Sr. Principal Ae - Verification Ip, Hpc Protocols

Cadence

San Jose, CA, US
Base: $143,500 to $266,500; bonus/equity: eligible...
8+ years design verification experience
Expertise in pcie, cxl, ucie protocols
Strong verilog and systemverilog skills
This role bridges the gap between Cadence's R&D and customers by providing technical expertise for the Verification IP portfolio

Job Summary

  • This role bridges the gap between Cadence's R&D and customers by providing technical expertise for the Verification IP portfolio.
  • The position requires driving business closure through product demonstrations, customer evaluations, and benchmarking to prove tool value.
  • Candidates will benefit from a competitive compensation structure including bonus, equity, and comprehensive benefits like 401(k) matching.

Matching Summary

This role bridges the gap between Cadence's R&D and customers by providing technical expertise for the Verification IP portfolio.

Salary

Base: $143,500 to $266,500; Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, holidays, 401(k) match, medical/dental/vision

Skills & Requirements

Must-have

  • 8+ years Design Verification Experience
  • Expertise in PCIe, CXL, UCIe protocols
  • Strong Verilog and SystemVerilog skills
  • UVM methodology proficiency
  • Pre-silicon debugging with waveform viewers

Nice-to-have

  • Mentoring junior engineers
  • Customer relationship building
  • Proactive problem solving approach
  • Global team collaboration skills
  • Continuous learning mindset

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering
  • 8+ years of Design Verification experience
  • Advanced programming skills in Verilog and SystemVerilog

Work Rights

Not specified

Tailored Resume

Cover Letter