Analog Mixed Signal Ic Design Principal Engineer

Marvell

Base: cad 164,000 - 218,700 py; bonus/equity: not ...
High speed analog mixed signal design
7nm and below tsmc process experience
Serdes architecture development
The candidate will lead the development of high-speed and high-performance SerDes in advanced technology nodes such as 5nm, 3nm, and 2nm

Job Summary

  • The candidate will lead the development of high-speed and high-performance SerDes in advanced technology nodes such as 5nm, 3nm, and 2nm.
  • This role involves designing critical IP including 224G/112G PAM4 interfaces and collaborating with DSP, Analog, and Digital teams on architecture.
  • Marvell offers a collaborative environment where engineers can learn multiple engineering aspects while diving deep into their specialization.

Matching Summary

The candidate will lead the development of high-speed and high-performance SerDes in advanced technology nodes such as 5nm, 3nm, and 2nm.

Salary

Base: CAD 164,000 - 218,700 per annum; Bonus/Equity: Not specified; Benefits: Competitive compensation and great benefits

Skills & Requirements

Must-have

  • High speed analog mixed signal design
  • 7nm and below TSMC process experience
  • SerDes architecture development
  • Layout instruction provision
  • IP characterization and validation

Nice-to-have

  • D2D and DDR experience
  • Collaborative team player
  • Project leading capabilities
  • SOC support experience
  • Mentoring others to improve

Key Requirements

  • Bachelor's degree plus 12+ years experience
  • Master's degree plus 8+ years experience
  • PhD plus 5+ years experience
  • Eligible for US export control access
  • Experience with 7nm and below processes

Work Rights

Must be eligible for US export-controlled information (Citizenship or PR required)

Tailored Resume

Cover Letter