Principal Engineer, Design Technology Co-optimization

Intel Retiree Medical Plan Trust

Hillsboro, Oregon, US
Base: $220,920.00-$311,890.00 usd annually; bonus/...
Hybrid
Standard cell library design expertise
Mosfet electrical characteristics knowledge
Spice circuit simulation proficiency
The role involves driving the optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs

Job Summary

  • The role involves driving the optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs.
  • Candidates will interface directly with key Intel foundry customers to identify technology gaps and drive co-optimization with technology development teams.
  • The position offers a competitive compensation package including stock bonuses, health benefits, retirement plans, and a hybrid work model.

Matching Summary

The role involves driving the optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs.

Salary

Base: $220,920.00-$311,890.00 USD annually; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, vacation

Skills & Requirements

Must-have

  • Standard cell library design expertise
  • MOSFET electrical characteristics knowledge
  • Spice circuit simulation proficiency
  • Advanced semiconductor technology understanding
  • Foundry ecosystem experience

Nice-to-have

  • Product signoff methodology familiarity
  • Pre and post Si benchmarking practices
  • Collaborative mindset and team player
  • Excellent oral and written communication skills
  • EDA tool design optimization experience

Key Requirements

  • Ph.D. or Master's degree in Electrical Engineering or Computer Science
  • 10+ years of industry experience
  • Position of Trust requiring extended background investigation

Work Rights

Not specified

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