Asic Engineering Technical Leader G11 | Rtl | Sta | Floor Planning | Physical Design Verification | Node Exp | 12-17 Years | 2008251

Cisco

Bangalore, India
Rtl to gds implementation
Static timing analysis
Physical design verification
You will drive the backend process through the entire RTL to GDS Implementation flow

Job Summary

  • You will drive the backend process through the entire RTL to GDS Implementation flow.
  • The role involves analyzing quality and efficiency gaps to improve physical design methodologies.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations.

Matching Summary

You will drive the backend process through the entire RTL to GDS Implementation flow.

Skills & Requirements

Must-have

  • RTL to GDS implementation
  • Static Timing Analysis
  • Physical Design Verification

Nice-to-have

  • Creative problem-solving skills
  • Collaboration with cross-functional teams
  • Experience with automation scripts

Key Requirements

  • 13+ years of ASIC engineering experience
  • Experience with large designs over 100M gates
  • Bachelor's or Master’s Degree in Electrical or Computer Engineering

Work Rights

Not specified

Tailored Resume

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