Asic Physical Design Engineer

Jane Street

London, United Kingdom
Not specified; not specified; not specified
On-site
8+ years hands-on asic physical design experience
End-to-end ownership of pd flows
Ability to read and write rtl code
This role is part of an Ultra Low Latency team where engineers collaborate across trading, networking, and research infrastructure

Job Summary

  • This role is part of an Ultra Low Latency team where engineers collaborate across trading, networking, and research infrastructure.
  • Candidates are expected to own the physical design flow end-to-end while thinking like chip designers who understand front-end decisions.
  • The company utilizes a custom hardware development toolchain called Hardcaml embedded in OCaml to improve productivity and reliability.

Matching Summary

This role is part of an Ultra Low Latency team where engineers collaborate across trading, networking, and research infrastructure.

Salary

Not specified; Not specified; Not specified

Skills & Requirements

Must-have

  • 8+ years hands-on ASIC physical design experience
  • End-to-end ownership of PD flows
  • Ability to read and write RTL code
  • Experience with Python or C++ programming
  • Understanding of front-end/back-end design boundaries

Nice-to-have

  • Interest in software engineering for hardware
  • Willingness to learn OCaml language
  • Experience working across the chip design stack
  • Background in smaller teams wearing multiple hats

Key Requirements

  • 8+ years of modern physical design flow experience
  • Fluent in English
  • No specific visa sponsorship mentioned

Work Rights

Not specified

Tailored Resume

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