Level 2: $91,800 to $124,200; level 3: $112,200 to...
Fpga design tools
Hardware description language (hdl)
High-speed serial interfaces (serdes)
Develop FPGA requirements, FPGA code of logic design, generate self-checking test bench, unit test, synthesis, timing analysis, Built-In-Test (BIT) and support of debug and system integration activities
Job Summary
Develop FPGA requirements, FPGA code of logic design, generate self-checking test bench, unit test, synthesis, timing analysis, Built-In-Test (BIT) and support of debug and system integration activities.
Develop, debug, and integrate processor subsystem features and interfaces in FPGA hardware for advanced processors, and develop high-speed serial interferences inside an FPGA (SERDES).
This position requires obtaining, after starting in the role, a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship.
Matching Summary
Develop FPGA requirements, FPGA code of logic design, generate self-checking test bench, unit test, synthesis, timing analysis, Built-In-Test (BIT) and support of debug and system integration activities.
Salary
Level 2: $91,800 to $124,200; Level 3: $112,200 to $151,800; Level 4: $136,850 to $185,150; Benefits: Variety of benefit programs available
Skills & Requirements
Must-have
FPGA design tools
Hardware Description Language (HDL)
high-speed serial interfaces (SERDES)
cross-functional collaboration
Digital Signal Processing
Nice-to-have
aerospace design techniques
troubleshooting and debugging
FPGA life cycle experience
industry best practices
Key Requirements
1+ years related experience (Level 2)
3+ years related experience (Level 3)
5+ years related experience (Level 4)
Bachelor of Science degree in Engineering, Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent
U.S. Citizenship required for security clearance
Work Rights
Must be a U.S. Person (U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee)