Design Verification Engineering Manager

Intel Retiree Medical Plan Trust

Austin, Texas, US
Base: $256,050.00-361,480.00 usd; bonus/equity: st...
Hybrid
Systemverilog/uvm development
Coverage-driven verification
Formal methods
Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation

Job Summary

  • Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation.
  • Define Project Specific Verification Strategy, including scalable and reusable verification plans, test benches, and environments for blocks, subsystems, and SoCs.
  • Collaborate closely with chiplet architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

Matching Summary

Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation.

Salary

Base: $256,050.00-361,480.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, vacation

Skills & Requirements

Must-have

  • SystemVerilog/UVM development
  • coverage-driven verification
  • formal methods
  • performance analysis
  • EDA tools
  • constrained-random testing
  • scripting languages

Nice-to-have

  • collaborative team culture
  • customer impacting technology
  • innovative methodologies
  • lean and efficient team
  • mentor emerging talent

Key Requirements

  • Bachelor's degree in STEM
  • 6+ years of ASIC/FPGA design verification
  • Strong OOP principles
  • UVM and/or Formal based verification architectures
  • Industry standard protocols (AMBA AXI/AXI-S/CHI, PCIe, Ethernet, UART, SPI, I2C/I3C)
  • Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium)
  • Strong debugging skills

Work Rights

Not specified

Tailored Resume

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