Asic Engineering Technical Lead :: Dft/mbist/atpg/scan Insertion :: Exp 12+ Years
Cisco UK
Bangalore, India
Dft/mbist/atpg/scan insertion
Jtag protocols, scan and bist architectures
Ate pattern debug
Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
Job Summary
Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Matching Summary
Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Skills & Requirements
Must-have
DFT/MBIST/ATPG/Scan Insertion
JTAG protocols, Scan and BIST architectures
ATE pattern debug
Gate level simulation and debug
Tcl, Python/Perl scripting
Nice-to-have
Innovative DFT IP development
Thrive in multifaceted environment
Collaboration with cross-functional teams
Key Requirements
10+ years of experience
Bachelor's or Master’s Degree in Electrical or Computer Engineering
Experience with ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime)