Senior Staff Logic Design Engineer

Altera Digital Health

New Delhi, India
Not specified; not specified; not specified
Fully remote
10+ years experience in electrical engineering
System verilog and vcs simulator expertise
Rtl coding and logic optimization skills
The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs

Job Summary

  • The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs.
  • Candidates must possess extensive experience with System Verilog, Synopsys tools, and various programming languages like C++ and Python.
  • The position requires involvement in the entire IP development flow from design example creation to hardware brings up and debugging.

Matching Summary

The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs.

Salary

Not specified; Not specified; Not specified

Skills & Requirements

Must-have

  • 10+ years experience in Electrical Engineering
  • System Verilog and VCS simulator expertise
  • RTL coding and logic optimization skills
  • C/C++/Perl/Python/TCL scripting proficiency

Nice-to-have

  • FPGA design and programming experience
  • RTL validation background
  • Strong communication and problem-solving skills

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 10+ years of professional engineering experience
  • Experience with Lint and Synthesis tools

Work Rights

Not specified

Tailored Resume

Cover Letter