Engineer Design Verification Engineer

Analog Devices Foundation

Bangalore, India
Systemverilog and uvm verification
Verification plans using vplanner
Module and system level verification
Plan and strategize to effectively verify a design (block as well as full-chip) by developing a thorough understanding of the design under test

Job Summary

  • Plan and strategize to effectively verify a design (block as well as full-chip) by developing a thorough understanding of the design under test.
  • Employ UVM based verification methodology and use assertions, functional/code coverage, and formal verification to reach verification goals.
  • Support post-silicon verification activities of the products working with design, product evaluation, and applications engineering teams.

Matching Summary

Plan and strategize to effectively verify a design (block as well as full-chip) by developing a thorough understanding of the design under test.

Skills & Requirements

Must-have

  • SystemVerilog and UVM verification
  • verification plans using vPlanner
  • module and system level verification
  • assertions and coverage
  • formal verification techniques
  • testbench development from ground up

Nice-to-have

  • mentoring and leading junior engineers
  • inter-personal and teamwork skills
  • proactive and result oriented
  • familiarity with DSP verification
  • processor based SoC design verification

Key Requirements

  • 8–12 years of experience in digital SoC verification
  • Proficient in System Verilog, UVM, C, Perl, Python
  • Knowledge of state-of-the-art verification techniques
  • Experience with testplan development
  • B.Tech/M.Tech. in EE/ECE

Work Rights

Not specified

Tailored Resume

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