Lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits
Job Summary
Lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits.
Conduct power integrity (IR drop), SNA and EM on top-level, and be responsible for floor planning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna).
Collaborate closely with architecture, RTL design, DFT, and package teams to ensure seamless integration and successful product delivery.
Matching Summary
Lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits.
Skills & Requirements
Must-have
power integrity analysis
static timing analysis
place and route
low power implementation
physical verification
EDA tools proficiency
Nice-to-have
mentoring junior engineers
cross-functional collaboration
EDA tool evaluation
scripting for automation
Key Requirements
9+ years of professional experience with Bachelor's degree
8+ years of professional experience with Master's degree
Working knowledge on advance tech nodes 16ff and below
Extensive knowledge in back-end implementation tasks
Expert-level proficiency with Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI