Senior Design Verification Engineer

Maravet

Westborough, MA, USA
Base: $108,500 - $160,510; bonus/equity: not speci...
System verilog for debugging
Synopsys vcs simulation
Python scripting
You will work day-to-day with an RTL engineer to verify their design using System Verilog and run simulations with Synopsys VCS or a similar program

Job Summary

  • You will work day-to-day with an RTL engineer to verify their design using System Verilog and run simulations with Synopsys VCS or a similar program.
  • Contribute as a Verification Engineer developing the next generation of cloud, networking, and security processors, working with Architects and Designers to develop complex verification environments.
  • Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage, including financial well-being, family support, mental and physical health, and recognition.

Matching Summary

You will work day-to-day with an RTL engineer to verify their design using System Verilog and run simulations with Synopsys VCS or a similar program.

Salary

Base: $108,500 - $160,510; Bonus/Equity: Not specified; Benefits: Comprehensive benefits package

Skills & Requirements

Must-have

  • System Verilog for debugging
  • Synopsys VCS simulation
  • Python scripting
  • Linux environment
  • Verilog or VHDL design

Nice-to-have

  • Detail-oriented and iterative design
  • Strong team communication
  • Contribute to next-gen processors
  • Work with architects and designers

Key Requirements

  • 2-3 years professional experience OR Master's/PhD
  • Bachelor's in EE or CE
  • Coursework in analog, Verilog/VHDL, circuits, computer architecture
  • Experience with simulation tools (Synopsys, Cadence, Mentor)
  • Ability to write and debug testbenches

Work Rights

Eligible to access export-controlled information

Tailored Resume

Cover Letter