Staff Layout Design Engineer

Ambarella

Not specified
3+ years mask design experience
Finfet tape-out experience required
Cadence virtuoso custom circuit tools
Ambarella is seeking a Staff Layout Design Engineer to join their mixed signal IP team, focusing on physical layout designs for mixed-signal IPs in sub-micron CMOS technologies. The ideal candidate should have extensive experience in layout design, particularly with FinFET technology, and be proficient in using Cadence tools

Job Summary

  • The role involves working closely with IP designers on physical layout for mixed-signal IPs using Cadence and Mentor tools.
  • Candidates must have validated experience running and debugging DRC, LVS, and EMIR verification flows with Calibre.
  • The position requires deep understanding of analog circuit layout concepts specifically in submicron CMOS technologies.

Matching Summary

Match Score: 85

Ambarella is seeking a Staff Layout Design Engineer to join their mixed signal IP team, focusing on physical layout designs for mixed-signal IPs in sub-micron CMOS technologies. The ideal candidate should have extensive experience in layout design, particularly with FinFET technology, and be proficient in using Cadence tools.

Skills & Requirements

Must-have

  • 3+ years mask design experience
  • FinFET tape-out experience required
  • Cadence Virtuoso custom circuit tools
  • Calibre DRC LVS EMIR debugging
  • Submicron CMOS analog layout concepts

Nice-to-have

  • High-speed SerDes design experience
  • Top level integration knowledge
  • Perl Python or SKILL scripting proficiency
  • Customizing DRC and LVS decks
  • Cross team collaboration skills

Key Requirements

  • BSEE degree required
  • 3+ years relevant mask design experience
  • Tape-out experience with FinFET technology
  • Proficiency in Perl, Python, or SKILL scripting

Work Rights

Not specified

Tailored Resume

Cover Letter