Principal Logic Design Engineer

Altera Digital Health

New Delhi, India
Fully remote
15+ years electrical engineering experience
System verilog and vcs simulator expertise
Rtl coding and logic optimization skills
The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs

Job Summary

  • The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs.
  • Candidates must possess extensive experience with System Verilog, Synopsys tools, and various scripting languages.
  • The position requires a deep understanding of the IP development flow from design to hardware brings up.

Matching Summary

The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs.

Skills & Requirements

Must-have

  • 15+ years electrical engineering experience
  • System Verilog and VCS simulator expertise
  • RTL coding and logic optimization skills
  • C/C++/Perl/Python/TCL scripting proficiency
  • IP block design and integration experience

Nice-to-have

  • FPGA design and programming background
  • RTL validation experience
  • Strong cross-team communication skills
  • Hardware debugging and failure analysis

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering
  • 15+ years of professional experience
  • Experience with Lint and Synthesis tools

Work Rights

Not specified

Tailored Resume

Cover Letter