Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure
Job Summary
Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Involve in IP design example brings up on hardware, hardware verification and failure debugging.
Matching Summary
Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
Skills & Requirements
Must-have
System Verilog RTL coding
VCS/Synopsys simulators
Lint and Synthesis
mixed-signal and high-speed IPs
full-chip designs integration
Nice-to-have
FPGA design and programming
RTL validation experience
problem solving skills
good communication skills
Key Requirements
10+ years experience
Bachelor's or Master's degree
Electrical Engineering, Computer Engineering, or related field