Cadence is seeking an ATE Test Engineering Architect to lead the development and deployment of production test solutions for complex SoCs in their Emulation Products. The role requires extensive experience in ATE test strategy, silicon debugging, and collaboration with cross-functional teams, making it suitable for experienced engineers passionate about silicon quality and scalable test solutions.
Base: $178,500 to $331,500 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k) match, medical/dental/vision
Must-have
Nice-to-have
Not specified