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Astera Labs is seeking an Analog Mixed-Signal IC Layout Lead Engineer to design advanced Bi-CMOS/CMOS products, focusing on chip layout and integration. The ideal candidate should have over 8 years of experience in high-speed analog IC layout and be proficient in Cadence tools.
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Job Summary
You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout.
You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk.
You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones.
Matching Summary
Match Score: 75
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Astera Labs is seeking an Analog Mixed-Signal IC Layout Lead Engineer to design advanced Bi-CMOS/CMOS products, focusing on chip layout and integration. The ideal candidate should have over 8 years of experience in high-speed analog IC layout and be proficient in Cadence tools.
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Skills & Requirements
Must-have
high-speed analog IC layout
Cadence Virtuoso
chip top-level integration
minimizing layout parasitics
reducing skew and crosstalk
EM/IR compliance
DRC, LVS, ANT, density rules
ESD and latch-up design practices
Nice-to-have
BiCMOS layout experience
device physics foundation
three-dimensional layout understanding
cross-functional team collaboration
Key Requirements
8+ years of experience in high-speed analog IC layout
Proven experience handling at least one chip top-level through tapeout
Cadence SKILL and TCL scripting experience highly recommended