Base: not specified; bonus/equity: not specified; ...
Systemverilog and uvm
Uvm-based verification environment development
Constrained random and assertion-based verification
Lead verification planning and execution for complex digital and mixed-signal designs, architecting advanced verification environments and driving innovation in verification approaches
Job Summary
Lead verification planning and execution for complex digital and mixed-signal designs, architecting advanced verification environments and driving innovation in verification approaches.
Provide technical guidance and mentoring to junior verification engineers, and drive effective collaboration with design teams on verification planning and issue resolution.
Contribute to verification methodology improvements and best practices development, while leading silicon bring-up efforts and post-silicon validation activities.
Matching Summary
Lead verification planning and execution for complex digital and mixed-signal designs, architecting advanced verification environments and driving innovation in verification approaches.
Salary
Base: Not specified; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
SystemVerilog and UVM
UVM-based verification environment development
constrained random and assertion-based verification