Job Summary

• Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Supports SoC customers to ensure high-quality integration and verification of the IP block and drives quality assurance compliance for smooth IP-SoC handoff.

Matching Summary

Skills & Requirements

Key Requirements

• IC validation experience
• FPGA architecture
• Verilog/System Verilog
• programming languages (Python, tcl, C, VBA, HTML)
• high speed test equipment

Work Rights