The role involves defining and owning SoC-level and IP-level verification strategy, methodology, and coverage goals
Job Summary
The role involves defining and owning SoC-level and IP-level verification strategy, methodology, and coverage goals.
The candidate will lead verification execution, develop and debug UVM-based verification environments, and drive DV closure on diverse IPs and subsystems.
This is a hands-on leadership position requiring strong technical skills, team mentoring, strategic planning, and collaboration with design teams.
Matching Summary
The role involves defining and owning SoC-level and IP-level verification strategy, methodology, and coverage goals.
Skills & Requirements
Must-have
ARM-based microcontrollers expertise
SoC-level verification strategy
SystemVerilog and UVM proficiency
Low-power design verification
Experience with multiple interface protocols
Gate-level and power-aware simulations
Functional safety and security compliance
Nice-to-have
Strong team leadership and mentoring
Excellent communication skills
Project management and organizational skills
Collaboration in fast-paced environment
Knowledge of Flash memory and security IPs
Familiarity with Analog IPs in microcontroller design
Key Requirements
15+ years SoC/IP verification experience
Successful tape-outs of multiple SoCs
Proficiency with Synopsys VCS, Cadence Xcelium, Mentor Questa
Bachelor’s or Master’s in Microelectronics or related field