Senior Asic Design And Sta Engineer

NVIDIA

Not specified; not specified; not specified
Hybrid
5+ years physical design experience
Rtl2gds and sta convergence
Synopsys primetime timing analysis
The role involves leading full chip and chiplet level STA convergence from early stages to signoff for high-speed networking silicon

Job Summary

  • The role involves leading full chip and chiplet level STA convergence from early stages to signoff for high-speed networking silicon.
  • Candidates will collaborate with logic design and DFT engineers to define constraints and optimize timing for various work modes.
  • NVIDIA offers a diverse, supportive environment where engineers can make a lasting impact on AI platforms and global technology.

Matching Summary

The role involves leading full chip and chiplet level STA convergence from early stages to signoff for high-speed networking silicon.

Salary

Not specified; Not specified; Not specified

Skills & Requirements

Must-have

  • 5+ years physical design experience
  • RTL2GDS and STA convergence
  • Synopsys Primetime timing analysis

Nice-to-have

  • Creative autonomous engineer
  • Team collaboration skills
  • High-speed communication devices

Key Requirements

  • B.Sc/M.Sc in Electrical or Computer Engineering
  • Proven RTL2GDS and STA design experience
  • Deep knowledge of timing concepts

Work Rights

Not specified

Tailored Resume

Cover Letter