Asic Dft Engineering Technical Leader | 12+ Years, Bangalore
Cisco
Bangalore, India
On-site
Jtag protocols and scan architectures
Memory bist and boundary scan experience
Atpg and eda tools like tetramax tessent
This role involves leading the Design-for-Test strategy for Cisco's groundbreaking Silicon One architecture used in core switching and routing products
Job Summary
This role involves leading the Design-for-Test strategy for Cisco's groundbreaking Silicon One architecture used in core switching and routing products.
The candidate will collaborate with front-end RTL and backend physical design teams to drive DFT requirements early in the complex chip design cycle.
Candidates must possess strong verbal skills to thrive in a multifaceted environment while crafting innovative hardware DFT solutions with minimal mentorship.
Matching Summary
This role involves leading the Design-for-Test strategy for Cisco's groundbreaking Silicon One architecture used in core switching and routing products.
Skills & Requirements
Must-have
Jtag protocols and Scan architectures
Memory BIST and boundary scan experience
ATPG and EDA tools like Tetramax Tessent
Gate level simulation with VCS
Post-silicon validation and debug skills
Tcl Python Perl scripting capabilities
Nice-to-have
Verilog design for custom DFT logic
DFT CAD development methodology
Test Static Timing Analysis expertise
Bare die and stacked die strategies
Minimal mentorship problem solving
Key Requirements
Bachelor's or Master's degree in Electrical or Computer Engineering
At least 10 years of experience in DFT and silicon engineering
Experience with Jtag protocols, Scan, and BIST architectures
Proficiency with ATPG tools including TestMax, Tetramax, and Tessent
Strong background in post-silicon validation and P1687 patterns